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JPEG 2000 Brochures
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FactSheet
BA109: HD/DCI JPEG 2000 Decoder
BA110: HD/DCI JPEG 2000 Encoder
BA115: JPEG decoder
BA116: JPEG encoder
BA129: Sub-frame latency JPEG 2000 decoder
BA130: Sub-frame latency JPEG 2000 encoder
BA317: DDR3, DDR2, Multi-Port Memory Controller
BA412: DES and 3-DES IP core
BA511: ARINC429 - DO254 Compliant
BA612A: AHB Multi-Channel DMA Controller
DCPB2120
DCPB2160
ProductSheet
BA411E: Multi-Purpose AES Crypto Engine
BA414E: Public Key crypto engine
Demo AES
EasyKey - Crypto engines
Video over IP demo
Video
Barco Silex at E-Smart 2011 - Smart-engine for cryptography
Barco Silex at NAB Show 2008
Barco Silex at RTS 2010
Barco Silex at RTS 2011 - Crypto
Barco Silex at RTS 2011 - JPEG 2000
Barco Silex at RTS 2012
Barco Silex on YouTube
White Paper
Addressing latency-critical applications with JPEG 2000
Enabling real-time JPEG 2000 with FPGA architectures
Functional Verification of an Electronic Module Designed for an Aeronautic DO-254 Application
Increase performance in video and image processing applications with FPGA integration
Kintex 7 FPGA family: High performance DDR3 memory throughput achieved by optimization of the memory controller
Smart Engine for Public Key cryptography
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