BA312 - Multi-Port AHB DDR-SDRAM controller
Description
General Description
For write operations, each AHB port has dedicated buffers to stack up the commands and the associated data. Any read command is treated with the highest priority to minimize the latency on the AHB busses connected to the SDRAM controller ports.
All commands are managed by a common arbiter. The BA312 is able to optimize the bandwidth to the external device by managing up to 4 open banks and by interlacing commands to different rows.
Scalability
The following parameters must be configured before synthesizing the DDR-SDRAM Controller IP to minimize the silicon footprint:
- Number of AHB Ports
- Data Rate: Single or double
- Memory Data Bus Width: 8, 16 or 32
- Buffers Size
Programmability
Some other parameters can be configured via the APB interface:
- Number of rows & columns
- SDRAM CAS Latency
- SDRAM Burst Length
- RBC (Row, Bank, Column) or BRC (Bank, Row, Column) Address Mapping
- AUTO PRECHARGE feature
Optional capabilities
In the case of the same set of external pins is shared with another memory controller (Static Memory Controller for instance), the BA312 is able to interface with an EBI (External Bus Interface).
One extra block including the DCM (Digital Clock Manager) and the entire logic to capture read data is used to interface the Memory Controller with an external SDRAM device. Depending of the technology (ASIC or FPGA) and the type of SDRAM (SDR or DDR), different solutions are possible.
The BA312 is DFI 1.0 compliant.
Features
DDR-SDRAM Interface
- Single Data Rate SDRAM and Double Data Rate SDRAM are supported
- Compatible to JEDEC standard (JESD79C for DDR). Supports Micron, Samsung and Infineon devices, among others
- DFI 1.0 Compatible
- Operates at frequencies up to 250 MHz (90nm)
- Programmable CAS Latency: 2, 2.5 or 3 clock cycles
- Automatically generates the SDRAM initialization sequence
- Supports up to 14-bit address bus
- Programmable row and column address bit widths up to:
- 14-bit row address (max. 16k rows)
- 11-bit column address (max. 2k columns)
- 2-bit bank address (max. 4 banks)
- Configurable Memory Data Bus
- Supports up to 4 chip select signals in the current version
- Programmable Burst Length
- Supports Auto Refresh mode, Self Refresh mode and power-down mode
- Supports all power-saving features (PASR, TCSR & Deep Power Down) for Mobile SDRAM
- NOP, READ, WRITE, ACTIVE, AUTO REFRESH, PRECHARGE and BURST TERMINATE commands fully supported
- Auto Precharge option supported
- The following parameters are programmable: tRAS, tRCD, tRRD, tRP, tWR, tWTR, tXSR, and tRC
- Supports 4 open banks.
- SDRAM module serial presence detect not supported
- Able to interface with an EBI (External Bus Interface)
AHB Interface
- Supports up to 8 AHB Ports
- AMBA AHB 2.0 bus-compatible
- Does not generate SPLIT, RETRY & ERROR responses on the AMBA bus
- Supports all types of AMBA bursts
- Supports AHB data width of 32 (+ narrow access on 16 or 8 bits)
- Supports AHB address width of 32 bits
- Management of two independent AHB ports
