Public Key IP Core for RSA, ECC, ECDSA and ECDH


A tiny or high-performance PK crypto engine for RSA, ECC and ECDSA. A 100% CPU offload solution available on ASIC and FPGA
Public Key IP Core for RSA, ECC, ECDSA and ECDH


Public Key cryptography is part of many security standards and is widely used to establish secure communication channels across unsecure open networks. Our Public Key IP core can be used in applications such as TLS/SSL, IPSec/VPN, Car2X communication, Wireless communication (BLE, ZigBee…). Public key cryptography is also a key element of a HSM (Hardware Security Module) which needs to generate asymmetric key pairs and sign/authenticate data at very high speed.

Hardware acceleration – 100% CPU off-load

Software solutions are often too slow and overload the CPU. Processor accelerators are often not flexible enough and hard to use efficiently. The Public Key IP Core is an efficient hardware accelerator offloading 100% of the asymmetric operations from the processor and really offering significant and valuable advantages.

The very flexible architecture, can support the following algorithms:

  • RSA, DH, DSA, CRT up to 4096 bits
  • ECC/ECDH/ECDSA in GF(p), GF(2m) up to 1024 bits (on NIST, Brainpool, Koblitz and others curves)
  • Rabbin-Miller, Key Generation
  • Apple Home Kit
    • Curve25519
    • EdDSA (also named Ed25519)
    • SRP
  • Protection against timing and power attacks (SPA/DPA)

The high-level of scalability of the Public Key IP Core enables ASIC and FPGA designers to get the best trade-off between area and performance. Ultra-fast configurations are available.

SW drivers and OpenSSL engine

SW API/drivers are provided to support higher-level operations combining other Crypto IP Cores (Hash, RNG, and AES). Linux drivers and OpenSSL engine area available to ease the integration at the application level.


ASIC, FPGA (Microsemi, Altera, Xilinx)



  • High-level of scalability with solutions implementing from 4 up to 256 multipliers
  • 100% CPU off-load (pre and post-processing included)
  • Portability: ASIC, Altera, Xilinx, Microsemi
  • RSA, CRT, DH, DSA (Digital Signature Algorithm) up to 4096 bits
  • ECC/EDCH/ECDSA in F(p) and F(2m) up to 1024 bits
    • Point addition/doubling/multiplication
    • NIST, Brainpool, Koblitz and others curves
  • Rabin-Miller Primality check, Key Generation
  • Apple Home Kit:
    • Curve25519
    • EdDSA
    • SRP
  • Arithmetic operations in both fields F(p) and F(2m)
    • Modular Addition/ Subtraction/ Multiplication/ Division/ Inversion/ Exponentiation
  • Optional add-on for protection against SPA/DPA
  • Control Interface: APB/AXI4-Lite compliant CPU Interface
  • Data interface: AHB/AXI Slave interface
  • Off-the-shelf and silicon-proven solution