PCIe end-point DMA for FPGA

The PCI Express (PCIe) Endpoint DMA is a highly configurable solution for any FPGA design requiring PCIe interfacing.pcie_dma_ip_core

The PCI Express (PCIe) Endpoint DMA is a highly configurable solution for any FPGA design requiring PCIe interfacing. It supports PCIe Gen 1, Gen 2 and Gen 3 interfaces, with up to 8 lanes. The DMA makes it easy to quickly transfer massive data between CPU and FPGA. The flexibility of the IP core enables many different use cases. The configuration of the Endpoint DMA can easily be adapted to the requirements of each project. The PCIe Endpoint DMA is already used in many applications such as Ethernet cards, high resolution image processing and others.

 

Technical Description

The PCIe Endpoint DMA is an assembly of multiple modules: the bridge, the translation layer, registers, DMA and interrupts. The Rx and Tx DMA modules can support both 32-bit and 64-bit address access. Each DMA is individually configurable on the fly. The Endpoint DMA IP core can be used to implement multiple functions. The multiple functions make it possible to have multiple PCIe endpoints with a single physical interface. The Interrupts module efficiently handles and transmits MSI-type interrupts.

 

Features

  • PCIe endpoint
  • Gen 1, Gen 2 and Gen 3
  • 1x, 2x, 4x and 8x
  • Up to 16 DMA controllers
  • Highly configurable
  • Altera FPGA
    • Cyclone V
    • Arria II & V
    • Stratix IV & V
  • Xilinx FPGA
    • Spartan- 6
    • Artix-7
    • Kintex-7
    • Virtex-7
  • Standard interfaces
    • AXI-4
    • Avalon
    • Simple streaming
  • Drivers
    • Windows
    • Linux
    • Support for ARM, PowerPC, x86
    • 32 and 64 bits

 

Reference: BA611