The Barco Silex JPEG IP (Intellectual Property) cores are intended for high-speed encoding and decoding of images according to ISO/IEC 10918-1 baseline coding standard.
The IP cores can be used with all Xilinx and Altera (Intel) FPGA families. Moreover, our JPEG cores are very compact and can fit in smallest FPGA devices.
The JPEG encoding/decoding doesn’t require external DDR memory. For this reason, it is the ideal IP core for many applications with a good compromise between the quality, latency, complexity and compression ratio.
The encoding quality is fully configurable during run-time, including custom entropy and quantization tables.
The simple FIFO-like interfaces and 100% synchronous structure of our JPEG IP cores make the integration very easy. The encoding and decoding of the image or video is handled autonomously by the IP core, without any CPU intervention.
Our JPEG IP cores are used in many applications including industrial imaging, high speed camera, datacenter and multimedia conferencing.
- Compliant with baseline JPEG (ISO/IEC 10918-1)
- Unrestricted image resolutions up to 64K by 64K.
- Chroma subsampling (4:4:4, 4:2:2, 4:2:0), grayscale and bayer support.
- Full header building and parsing capability:
- user-definable comments
- application markers
- quantization tables
- Huffman tables
- Support for full-format and abbreviated-format, including restart markers and restart interval
- One-pass encoding scheme with bit rate regulation if enabled
- BA115: JPEG Baseline decoder
- BA116: JPEG Baseline encoder